1. Field of the Invention
The present invention relates to semiconductor memories, and more particularly, to a DRAM wherein more than one layer of metalization is used in strapping polysilicon word lines.
2. Description of the Related Art
Semiconductor dynamic random access memory (DRAM) devices or systems using dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static random access memory (SRAM) cells (e.g., 6-transistor (6T cells), or 4-transistor/2-resistor (4T/2R) cells). Such DRAM arrays historically have had lower performance than SRAM arrays. Consequently, system designers typically have chosen DRAM arrays when high density and low cost are required, such as for CPU main memory applications. Conversely designers typically have chosen SRAM arrays when higher performance is required, such as for cache memory and high speed buffer applications.
The reasons often cited for the lower performance of DRAM include: the destructive sensing of all memory cells common to the addressed word line (encountered in virtually all dynamic memory arrays); resulting in the need to restore data back into each sensed memory cell during the active cycle; the need to equilibrate bit lines and various other differential nodes; the need to precharge various circuit nodes between active cells; the need to bootstrap the selected word line above the supply voltage; the delay along the length of the word line and the requirement for periodic refreshing of all dynamic memory cells.
Generally, the memory cells are interconnected by bit lines or columns and word lines or rows. These lines are defined in a polysilicon layer of the memory device. Word lines implemented only in polysilicon layers, however, often have unacceptable delays in signal propagation, especially when high speed operation is desired.
In DRAMs, attempts to improve performance with word line strapping are limited by the fact that polysilicon word lines may be placed closer together ("pitched"), than metal lines may be "pitched." One approach to overcome this pitch problem in DRAMs includes providing a row decoder with a metal "word line" for every four rows. Local final decoders distributed along the metal "word line" drive a selected one of four relatively short polysilicon word lines when its metal "word line" is selected. By using such a row decoder with distributed final decoders, smaller transistors need to be used in the final decoders because there is not enough room for larger transistors. Therefore, while this solution may improve performance, it is still generally slow with regard to many of today's applications.